Compared with Class A/B amplifier, class d Pa amplifier
has poor audio performance. It not only has large distortion, but also has narrow dynamic range. Therefore, the current designer of class d Pa amplifier must improve its performance. By integrating high-performance sampling rate converter (SRC) and_-processing technology, the new generation of solutions can greatly improve the distortion (THD+N), and the dynamic range is over 100 dB.
Nowadays, one of the noise sources of class d Pa amplifier is the jitter of the audio sampling clock. Clocks are usually generated by SOC (MPEG decoder, DSP, etc.). Even small jitter can rapidly affect the performance of conventional class D amplifiers, because the audio clock is associated with the output clock of the modulator.
One way to solve this problem is to use SRC technology. Because SRC uses locally stable clock sources to synchronize digital audio clocks, such as quartz crystal oscillators, So the output jitter of the modulator is actually independent and unrelated to other audio clocks. Another advantage of SRC is that the output switching ratio of SRC is fixed no matter how the sampling rate of input audio fluctuates, which is different from that of PLL-based modulator. When the audio input source changes or the input clock is missing, SRC also improves the system's durability by eliminating audible noise.
Similar to the current high-end DAC technology, the audio quality of class d Pa amplifier has been improved by integrating high-order-processing technology. The modulator based on Δ-Σ technology can reduce the internal feedback of modulation error. By reducing the sampling error, the modulator can improve the output distortion and obtain better sound quality.